The present invention relates to analog-to-digital converters (ADCs), in particular to continuous-time delta-sigma modulators (CTDSMs).
CTDSM technology is gaining popularity due to its power-efficient operation well suited for high-speed, high-performance systems. In a CTDSM, typically an input analog signal, which can vary continually over time, is converted to a coarse high data rate digital stream, which represents the input with high fidelity in the frequency band of interest. This high data rate digital stream then goes through digital post-processing (typically decimation) to provide the final low data rate digital code stream which represents the analog input signal in digital domain with high fidelity.
Conventional CTDSMs use a current DAC in a feedback path of the modulator. Current DACs can suffer from content-dependent errors. Specifically, switch changes may occur in circuit elements of the DAC when the digital code input to them changes, which may generate a virtual ground glitch. However, when the digital code input to the unit cell does not change, such glitches do not appear. These error are content-dependent because they vary based on the digital codes that are input to the current DAC.
Quad-switching is a known technique to mitigate these types of glitches. In a quad-switched DAC, “dummy” switching may be induced in all unit cells of the DAC, regardless of whether the content being input to those unit cells changes or not. Thus, glitch errors are expected to be generally consistent in the current DAC and independent of the content that is input to it.
Although quad-switching helps to mitigate content-dependent errors in current DACs, which typically are considered AC operations, current DACs also suffer problems due to DC errors that are generated by the unit cells. Therefore, the inventors recognized a need in the art for linear CTDSM architectures that have high DC and AC performance.